Warning: [4] C:/Quartus/Reg_N_con_test_bench/test_reg.vhd(56): (vcom-1207) An abstract literal and an identifier must have a separator between them.
Questo è il codice utilizzato
- Code: Select all
------------------------------------------ Registro a N bit ------------------------------------------
--------------------------- con reset ed enable sincroni con il clock --------------------------------
-- Librerie --
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------------------------------------
-- Entità --
entity Reg_N is
generic(num_bit : integer :=10);
port(
clk : in std_logic ;
reset : in std_logic;
en : in std_logic;
d : in std_logic_vector(num_bit-1 downto 0);
q : out std_logic_vector(num_bit-1 downto 0)
);
end Reg_N;
------------------------------------------------------------------------------------------------------
-- Ricorda che Tclk <= Td/2 (per assicurarsi di prendere tutti i valori in ingresso(d))
------------------------------------------------------------------------------------------------------
-- Architettura --
architecture Reg_N of Reg_N is
begin
process(clk) -- reset ed enable sincroni con il clock
begin
if rising_edge(clk) then
if (en='1') then
if (reset='0') then
q<=d;
elsif(reset='1') then
q<=(others =>'0');
end if;
end if;
end if;
end process;
end Reg_N;
-------------------------------------------------------------------------------------------------------
e questo è il test bench:
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----------------------------------- Test bench del Registro a N bit -----------------------------------
-- Librerie --
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------------------------
-- Entity vuota per il test bench --
entity test_reg is
end test_reg;
-------------------------------------------------------------------------------------------------------
architecture test_reg of test_reg is
-- Component --
component Reg_N
port(
clk : in std_logic ;
reset : in std_logic;
en : in std_logic;
d : in std_logic_vector(10-1 downto 0);
q : out std_logic_vector(10-1 downto 0)
);
end component;
-------------------------------------------------------------------------------------------------------
-- Segnali --
signal my_clk : std_logic;
signal my_reset : std_logic;
signal my_en : std_logic;
signal my_d : std_logic_vector(10-1 downto 0);
signal my_q : std_logic_vector(10-1 downto 0);
-------------------------------------------------------------------------------------------------------
begin
blocco1: Reg_N
port map(my_clk, my_reset, my_en, my_d, my_q);
test_clk: process -- processo per il segnale di clock, Tclock = 100 ps ---> fclock = 10 GHz
begin
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps;
my_clk<='0';
wait for 50ps;
my_clk<='1';
wait for 50ps; -- finestra di osservazione del clock pari a 1050ps
end process test_clk;
test_res : process -- processo per il segnale di reset
begin
my_reset <='1';
wait for 250ps;
my_reset<='0';
wait;
end process test_res;
test_en : process -- processo per il segnale di enable
begin
wait for 20ps;
my_en<='1';
wait;
end process test_en;
test_d : process -- processo per il segnale di ingresso
begin
my_d<="1111111111";
wait for 210ps;
my_d<="0011110101";
wait for 210ps;
my_d<="0101011011";
wait for 210ps;
my_d<="0011000101";
wait for 210ps;
my_d<="1111011011";
wait for 210ps;
my_d<="0111010000";
wait;
end process test_d;
test_out : process -- processo per il segnale di uscita
begin
wait for 160ps;
assert(my_q = "0000000000")
report "errore resettaggio"
severity warning;
wait for 150ps;
assert(my_q = "0011110101")
report "errore 1"
severity warning;
wait for 200ps;
assert(my_q = "0101011011")
report "errore 2"
severity warning;
wait for 200ps;
assert(my_q = "0011000101")
report "errore 3"
severity warning;
wait for 200ps;
assert(my_q = "1111011011")
report "errore 4"
severity warning;
wait for 200ps;
assert(my_q = "1111011011")
report "errore 5"
severity warning;
wait;
end process test_out;
end test_reg;
-------------------------------------------------------------------------------------------------------
Da notare che i warning che io ho indicato nel test bench non compaiono siccome funziona tutto bene. Però
mi esce il warning che ho sopra indicato e che non riesco a risolvere.
Ciao
